1. Field of the Invention
The present invention relates to a charge transfer device and a method of driving the same, and a solid-state imaging device and a method of driving the same.
2. Description of the Related Art
In recent years, higher quality cameras have been demanded in the field of an animation picture camera and a still picture camera.
Although, generally the number of picture elements of an imaging device is increased to raise the quality of such a picture, an increase of the number of picture elements delays a transfer rate upon frame transfer of a signal charge of the picture element or a so-called frame rate. Consequently, in an auto focus (AF: auto focus control) camera using output signals of an imaging device, an auto iris (AE, auto exposure control) camera, auto white balance (AWB) camera and the like, the feedback is delayed or it may be difficult to follow a motion of a camera or a movement of an object when a composition is determined while seeing an animation output in an electronic still camera.
FIG. 1 is a plan view of an example of a CCD imaging device 51 to be used in such a camera. This CCD imaging device 51 transfers a signal charge in a so-called inter-line transfer method. In this imaging device, a plurality of light receiving units 52 made of a photo sensor are arranged in a matrix configuration. Each column of the light receiving units 52 is connected to a vertical CCD register 54 through a reading gate portion 53, and the vertical CCD registers 54 are connected to a horizontal CCD register 55. Charges from the horizontal CCD register 55 are converted through an output circuit such as an amplifier 56 or the like a voltage and then outputted as an output voltage Vout.
In the vertical ccD register 54, vertical drive pulses xcfx86V1, xcfx86V2, xcfx86V3, xcfx86V4 are applied to its transfer electrode and the signal charges are transferred in the 4-phase driving.
On the other hand, in the horizontal CCD register 55, horizontal drive pulses xcfx86H1, xcfx86H2 are applied alternately to the transfer electrodes arranged corresponding to each column of the respective light receiving unit and the signal charges are transferred in the 2-phase driving as described later.
To solve the above problem, that is, to raise the frame rate, it can be considered to increase the driving frequency of the CCD register of the CCD imaging device or the system. However, if the driving frequency is increased, its power consumption will resultantly increase.
In the CCD imaging device, a correlated double sampling (CDS) is carried out so as to cancel a reset noise or the like. If the driving frequency is raised, a necessity of carrying out the phase adjustment of sampling hold pulse in this sampling arises so that production efficiency drops.
As a means for making a horizontal scanning period half without increasing the data rate from the CCD imaging device, there are a method of adding two horizontal picture elements by floating diffusion (FD) by doubling the drive frequency of the horizontal CCD register and a method of adding two picture elements at the final stage by doubling the drive frequency of a stage other than the final stage of the horizontal CCD register. However, in any cases, the shape of output waveform is changed, so that the preset period or data period of the output waveform which can be sampled by the correlated double sampling or the like is reduced.
FIG. 2 shows a configuration of a 2-phase drive horizontal CCD register of the CCD imaging device 51 shown in FIG. 1 and its potential in the transfer direction. FIG. 3 shows the drive pulses xcfx86H1, xcfx86H2 and the CCD output waveform upon a normal operation of the horizontal CCD register.
In the horizontal CCD register 55, as shown in FIG. 2, a plurality of transfer electrodes 57 comprising a storage electrode 57s made of multi-crystal silicone of a first layer, and a transfer electrode 57t made of multi-crystal silicone of a second layer are arranged on a semiconductor substrate through an insulation film in the electrode transfer direction so as to form a plurality of transfer portions. A first phase drive pulse xcfx86H1 is applied to the transfer electrode 57 of every second transfer portion, and a second phase drive pulse xcfx86H2 is applied to the transfer electrode 57 of every other transfer portion, so that the signal charge is transferred by a so-called 2-phase complementary drive.
That is, as shown in FIG. 2, at a time point T1, the first phase drive pulse xcfx86H1 becomes a high level while the second phase drive pulse xcfx86H2 becomes a low level, so that the potential of the transfer portion to which xcfx86H1 is to be applied becomes deep and then a signal charge e is transferred thereto.
Next, at a time point T2, the first phase drive pulse xcfx86H1 becomes a low level while the second phase drive pulse xcfx86H2 becomes a high level, so that the potential of the transfer electrode portion to which xcfx86H2 is to be applied becomes deep and hence the signal charge is transferred from the transfer portion to which xcfx86H1 is to be applied to the transfer portion to which xcfx86H2 is to be applied.
In this manner, the signal charges are successively transferred in the transfer direction by the 2-phase drive pulses xcfx86H1, xcfx86H2.
The transfer portion at the final stage of the horizontal CCD register 55 is so constructed that the first phase drive pulse xcfx86H1 is applied thereto. At the time point T2, the signal charge is transferred from the horizontal CCD register 55 to the floating diffusion (FD) (not shown) and converted to a signal voltage.
After a signal is read through the floating diffusion (FD), a reset gate pulse xcfx86RG is applied to a reset gate portion adjacent to the floating diffusion (FD) so that the charge of the floating diffusion (FD) is reset.
Thus, a CCD output waveform shown in FIG. 3 is obtained.
A portion Tp in the CCD output waveform is a section which indicates a preset signal and a portion therein Td is a section which indicates a data signal.
As for the output signal from the CCD imaging device, generally so as to improve an S/N ratio, first the correlated double sampling, that is, the preset signal Tp is clamped and then the data signal portion Td is sampled.
Meantime, if the number of picture elements is increased to improve the picture quality, a fetch speed of one picture screen, that is, a so-called frame rate is retarded, so that feedback of AF, AE, AWB or the like using the CCD output signal is delayed or it becomes difficult to display the same on a liquid crystal screen or the like to confirm its composition.
To improve such a defect, there is a method of doubling the drive frequency of, for example, the horizontal CCD register so as to quicken the output data rate.
FIG. 4 shows a horizontal drive pulse and a CCD output waveform of this case.
Because the drive frequency is doubled, the wavelengths of the horizontal drive pulse xcfx86H1, xcfx86H2 and the reset gate pulse xcfx86RG become half respectively and the period of the CCD output waveform also becomes half.
However, in this case, widths Tp2, Td2 of the portions for carrying out the clamp or sampling become half as compared to a usual case, so that the phase of a clamp pulse or sampling pulse needs to be adjusted one by one thereby reducing production efficiency.
Further, because the data rate doubles, the signal processing speed also doubles so that power consumption and noise increase. Further, because the system design is limited, disadvantage arises in production cost.
On the other hand, as a method of doubling the scanning speed of the horizontal CCD register without changing the data rate, there is a method of adding signal charge of two horizontal picture elements at the floating diffusion (FD).
FIG. 5 shows a horizontal drive pulse and a CCD output waveform of this case.
According to this method, the lengths of a preset period Tp3 and a data period Td3 become half as compared to the usual case like Tp2 and Td2, respectively. Therefore, the phases of the clamp pulse and sampling pulse must be adjusted.
This is because Tp3 is limited by the high level period of a first time of the horizontal drive pulse xcfx86H1 and Td3 is limited by the low level period of a second time of the horizontal drive pulse xcfx86H1.
FIG. 6 is a sectional view showing the horizontal transfer register of a solid-state imaging device, for example, a CCD area sensor. Referring to FIG. 6, an N type transfer channel 103 is formed on the surface side of an N type substrate 101 with a P type well 102 disposed therebetween. On the N type transfer channel 103 are arranged gate electrodes 104, 105 of first and second layers, which are formed of polysilicone or the like through a gate insulating film (not shown), alternately in the portion direction.
In the surface portion of the transfer channel 103 below the gate electrode 105 is ion-implanted an N- impurity. The gate electrodes 104, 105 ,of the first and second layers adjacent to each other serve as a pair and horizontal transfer clocks xcfx86H1, xcfx86H2 having opposite phase to each other as shown in FIG. 7 are applied to each pair of the gate electrodes 104, 105 alternately. The horizontal transfer clocks xcfx86H1, xcfx86H2 carry out complementary drive for the horizontal transfer register.
A transfer operation on the horizontal transfer register having the aforementioned structure will be described with reference to a potential diagram shown in FIG. 8. FIG. 8 shows potential distribution at each of timings T1-T4 of FIG. 7.
Because the horizontal transfer clock xcfx86H1 of the first phase is of high level (hereinafter referred to as xe2x80x9cHxe2x80x9d level) while the horizontal transfer clock xcfx86H2 of the second phase is of low-level (hereinafter referred to as xe2x80x9cLxe2x80x9d level) when T=T1, the potential under the gate electrodes 104, 105 of xcfx86H1 becomes deep. Further, because the potential under the gate electrode 104 is deeper than the potential under the gate electrode 105, the signal charge is accumulated under the gate electrode 104 of xcfx86H1.
When T=T2, the horizontal transfer clock xcfx86H1 of the first phase is of L level and the horizontal transfer clock xcfx86H2 of the second phase is of H level. Thus, the potential under the gate electrodes 104, 105 of xcfx86H1 becomes shallow and the potential under the gate electrodes 104, 105 of xcfx86H2 becomes deep. Consequently, the signal charge accumulated under the gate electrode 104 of xcfx86H1 is transferred to the gate electrodes 104, 105 of xcfx86H2. Because the potential of the portion under the gate electrode 104 is deeper than the potential of the portion under the gate electrode 105, the signal charge is accumulated under the gate electrode 104 of xcfx86H2.
When T=T3, the horizontal transfer clock xcfx86H1 of the first phase is of H level and the horizontal transfer clock xcfx86H2 of the second phase is of L level. Thus, the potential under the gate electrodes 104, 105 of xcfx86H1 becomes deep and the potential under the gate electrodes 104, 105 of xcfx86H2 becomes shallow. Further, because the potential of the portion under the gate electrode 104 is deeper than the potential of the portion under the gate electrode 105, the signal charge accumulated under the gate electrode 104 of xcfx86H2 is transferred to the gate electrodes 104, 105 of xcfx86H1 and accumulated under the gate electrode 104.
After T=T4, the same operation is repeated. By this series transfer operation, the horizontal transfer of the signal charge by one horizontal picture element is carried out in one cycle of the horizontal transfer clocks xcfx86H1, xcfx86H2. The signal charge transferred horizontally is supplied successively to a charge detecting portion (not shown) through a horizontal output gate and converted to a signal voltage at this charge detecting portion so as to produce a CCD output.
However, the CCD sensor has a problem that the frame rate drops with a tendency of increased picture elements in recent years. If the frame rate drops, feedback at the time of photometry upon exposure adjustment is delayed in, for example, a camera system equipped with the CCD area sensor. Further, if the frame rate drops, the signal charge accumulation time is prolonged, so that deterioration of picture quality due to a dark signal is a problem to be solved.
As a method for increasing the frame rate in a multi-picture element CCD area sensor, there are a method of selectively reading the signal charge from picture element in the vertical direction and a method of thinning lines in the vertical direction by selectively throwing out the signal charge transferred from the vertical transfer register to the horizontal transfer register in the unit of each line, to a charge discharging portion provided beside the horizontal transfer register.
On the other hand, as a method for increasing the frame rate by reducing the output period of one horizontal line (1H), there is only a method of raising the frequency of the horizontal transfer clocks xcfx86H1, xcfx86H2 for driving the horizontal transfer register, that is, the horizontal drive frequency. However, if the horizontal drive frequency is raised, power consumption is increased and further in a signal processing system at the following step, clamp or sampling margin diminishes so that the CDS (correlated double sampling) becomes difficult.
In view of such aspects, it is an object of the present invention to provide a CCD imaging device which can make waveforms of outputs from the CCD imaging device upon a normal drive and an N-time speed drive and can carry out the sampling with sufficiently securing a period for a correlated double sampling and which reduces a horizontal scanning period to thereby make a feedback of an automatic control and a monitor output faster and is suitable for high picture quality by increasing the number of pixels.
It is another object of the present invention to provide a charge transfer device which can reduce an output period without changing a drive frequency and to provide a solid-state imaging device which can increase a frame rate resulting from reduction of an output period of one horizontal line by using the above charge transfer device as a horizontal transfer register.
According to a first aspect of the present invention, a charge transfer device having a charge transfer portion in which a plurality of electrode pairs are formed above a transfer channel includes means for commonly wiring the plurality of electrode pairs forming N (N=2, 3, 4, . . . natural numbers) bits of the charge transfer portion so that electrode pairs of each half bit can be independently, driven at every N bits, means for, in a normal operation, inputting the electrode pairs of each half bit with the same drive pulse to operate it by a two-phase complementary drive, and means for, in an N-time speed operation, inputting the electrode pairs of N bits with N pairs of complementary drive pulses to operate them by a 2N-phase complementary drive.
According to a second aspect of the present invention, a method of driving a charge transfer device having a charge transfer portion in which a plurality of electrode pairs are formed above a transfer channel and arranged such that the plurality of electrode pairs forming N (N=2, 3, 4, . . . natural numbers) bits of the charge transfer portion are wired at every N bits so that electrode pairs of each half bit can be independently driven at every N bits, includes a step of, in a normal operation, inputting the electrode pairs of each half bit with the same drive pulse to operate it by a two-phase complementary drive, and a step of, in an N-time speed operation, inputting the electrode pairs of N bits with N pairs of complementary drive pulses to operate them by a 2N-phase complementary drive.
According to a third aspect of the present invention, a charge transfer device, includes an electrode structure formed of electrode pairs for first and second phases repeatedly and alternately arranged above a transfer channel in its transfer direction of and arranged such that the electrode pairs for the first phase located across the electrode pairs for the second phase can be independently driven, means for applying a DC voltage to the electrode pairs for the second phase, and means for supplying transfer clocks having a phase reverse each other to each of the electrode pairs for the first phase located across each of the electrode pairs for the second phase.
According to a fourth aspect of the present invention, a solid-state imaging device includes an imaging unit formed of a plurality of pixels for converting incident light into signal charges, and a charge transfer portion for transferring the signal charges read out from the plurality of pixels. The charge transfer portion having an electrode structure formed of electrode pairs for first and second phases repeatedly and alternately arranged above a transfer channel in its transfer direction of and wired such that the electrode pairs for the first phase located across the electrode pairs for the second phase can be independently driven, a mode setting unit for setting an operation mode, and means for, when the mode setting unit sets a first operation mode, supplying a DC voltage or a transfer clock having a phase reverse to that of the transfer clock for the first phase to the electrode pair for the second phase and supplying a transfer clock having the same phase as that of the transfer clock to each of the electrode pairs located across the electrode pair for the second phase and for, when the mode setting unit sets a second operation mode, applying a DC voltage to the electrode pairs for the second phase and supplying the transfer clock having the reverse phase to each of the electrode pairs for the first phase located across the electrode pair for the second phase.
According to a fifth aspect of the present invention, a method of driving a solid-state imaging device which has an imaging unit formed of a plurality of pixels for converting incident light into signal charges, and a charge transfer portion for transferring the signal charges read out from the plurality of pixels and in which the charge transfer portion has an electrode structure formed of electrode pairs for first and second phases repeatedly and alternately arranged above a transfer channel in its transfer direction of and wired such that the electrode pairs for the first phase located across the electrode pairs for the second phase can be independently driven, includes a step of, in a first operation mode, supplying a DC voltage or a transfer clock having a phase reverse to that of a transfer clock for the electrode pairs for the first phase to the electrode pairs for the second phase and supplying a transfer clock having the same phase as that of the transfer clock to each of the electrode pairs located across the electrode pair for the second phase, and a step of, in a second operation mode, applying a DC voltage to the electrode pairs for the second phase and supplying transfer clocks having the reverse phase to each of the electrode pairs for the first phase located across the electrode pair for the second phase.